1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, such as bare dice or dice contained on a wafer. More specifically, the present invention relates to an improved apparatus and method for providing electrostatic discharge protection to a test fixture which is electrically connected to a semiconductor device during burn-in and/or testing.
2. Background of Related Art
It is well known that electrostatic discharge (ESD) can damage semiconductor devices. Thus, ESD protection circuits are typically integrated into a semiconductor die to protect the input and output circuitry. Exemplary ESD protection circuitry located between a bonding pad and internal circuitry of a semiconductor device are disclosed in U.S. Pat. No. 5,500,546, issued Mar. 19, 1996, entitled “ESD Protection Circuits Using Zener Diodes,” to Marum et al. and in U.S. Pat. No. 6,040,733, issued Mar. 21, 2000, entitled “Two-stage Fusible Electrostatic Discharge Protection Circuit,” to Casper et al.
In order to conserve the amount of surface area, or “real estate,” consumed on a die, ESD circuitry may not always be included as part of the die. In such a case, ESD protection is typically included in the packaging for the die or in higher-level packaging, as when the die is used to construct multi-chip modules or other semiconductor die-based devices.
Bare (i.e., unpackaged) dice may be burned-in and tested during the manufacturing process to ensure that each die is a known good die (KGD). For burn-in and testing, a bare die is placed in a carrier which provides a temporary electrical connection with the bond pads of the die for interconnection with external test circuitry. Akram et al., in U.S. Pat. No. 6,018,249, issued Jan. 25, 2000 (hereinafter “Akram '249”), which is assigned to the assignee of the present invention and hereby incorporated herein in its entirety by this reference, discloses a test system for testing semiconductor components which includes an interconnect for making temporary electrical connection with the semiconductor components.
Further, Akram et al., in U.S. Pat. No. 6,016,060, issued Jan. 18, 2000 (hereinafter “Akram '060”), which is assigned to the assignee of the present invention and hereby incorporated herein in its entirety by this reference, discloses an interconnect for temporarily establishing electrical communication with semiconductor components having contact bumps. FIG. 1 shows one embodiment of test fixture disclosed in Akram '060. As shown in FIG. 1, that test fixture, which is referred to in Akram '060 as “interconnect 20,” includes a substrate 24 and a plurality of contact members 22 arranged on substrate 24 50 as to contact and electrically engage the bond pads of a semiconductor device (not shown) to be burned-in or tested. Each contact member 22 is electrically connected to a corresponding contact pad 31 of the test fixture (interconnect 20) through a conductor 30. The contact pads 31 are configured to provide an electrical connection from external test circuitry (not shown) to the bond pads of the semiconductor device.
Handling of a bare semiconductor device, or die, without internal ESD protection circuitry during burn-in and test processes can destroy the semiconductor device. To protect semiconductor devices from ESD damage, state-of-the-art test carriers, such as those disclosed in U.S. Pat. No. 6,136,137 to Farnworth et al. and U.S. Pat. No. 6,099,597 to Yap et al., include conductive metal surfaces that conduct built-up electrostatic charges away from carrier surfaces which touch, or are in close proximity to, the bare semiconductor devices.
Test fixtures that include ESD protection circuitry placed thereon so as to protect the input and output bond pads of a bare semiconductor device without its own internal ESD protection circuitry are not known in the art.